Recently, the semiconductor industry has developed so rapidly that semiconductor devices almost extend into the sub-micron level. When either increasing integration density of a device or reducing its chip area, it becomes crucial to maintain an unchanged capacitance per cell especially for dynamic random access memory (DRAM) scaling. The lower limit for capacitances of storage capacitors is currently considered to be at least 25 fF.
Increasing the surface area of a capacitor and implementing of high-k dielectrics would improve the performance of capacitance. A promising material, hemispherical grained silicon (HSG), has been extensively used to increase the surface area of a capacitor and also has been widely applied to stacked DRAMs. However, employing HSG in trench DRAMs is not feasible, because the physical property of HSG is quite similar to that of single crystalline silicon, which would cause inevitable damage of trench sidewalls while removing the upper part of the HSG layer in the deep trench by wet etching.
Growing an etch stop layer before forming a HSG layer may solve the problem mentioned above. Unfortunately, any etch stop layer existing between the HSG layer and the trench would deteriorate capacitance enhancement due to the parasitic series capacitance thereof. In attempted resolution of this issue, some processes have been studied to integrate successfully HSG into trench DRAMs. One of the commonly used processes is to employ an oxide layer as an etch stop layer. In this process, an oxide layer is formed on the bottom and two sides of the trench prior to a HSG layer, and several steps are subsequently performed to strip off the oxide layer on the bottom of the trench, that is, to keep the oxide layer on only the top part of the trench. Nevertheless, the process is very complicated and therefore quite difficult.